1. Field of the Invention
The present invention relates to a drive unit and a liquid crystal device using the same drive unit. More particularly, the invention relates to a drive unit having a memory for storing display data from a microprocessor unit and to a liquid crystal device using the same drive unit.
2. Background Art
So far, as a signal line driver (drive unit) applicable to liquid crystal device, there has been known a signal line driver which internally incorporates a memory for storing display data. The use of this signal line driver enables display of an image through the use of display data in a built-in memory without transferring display data from an external microprocessor unit (which will hereinafter be referred to suitably as an MPU) on occasion; therefore, the power consumption is considerably reducible in display of static images.
In connection with such a memory-incorporated signal line driver (column driver), there exists an MPU access request (first access request) forming a request for access to a memory according to a command from an MPU and an LCD access request (second access request) forming a request for access to a memory according to a displaying operation in an LCD (displaying section). Additionally, the LCD access request takes place in synchronism with periodic timings for liquid crystal display, while the MPU access request is made in asynchronous relation to the liquid crystal display timings. For this reason, there is a possibility that these access requests take place competitively.
One possible solution to such a competition between the access requests is use of a dual-port memory as an incorporated memory of a signal line driver. This dual-port memory has two data ports which are accessible simultaneously. Accordingly, even if the competition between access requests comes about, the read/write operation is achievable properly in the memory.
However, the cell size of such a dual-port memory is extremely larger than that of a single-port memory; in consequence, the use of the dual-port memory as an incorporated memory enlarges a chip area of the signal line driver, thereby increasing the price of the signal line driver.
Meanwhile, as a conventional means utilizing a single-port memory but capable of eliminating the problem in a competition between access requests through contrivance of circuit arrangement, there has been known a technique disclosed in Japanese Unexamined Patent Publication No. 10-105505.
There is a problem arising with this conventional technique, however, in that, when the sum of a processing time of an access operation according to an MPU access request and a processing time of an access operation according to an LCD access request is taken as T, there is a need to set the interval in time between MPU access requests at T, not only at a competition between access requests but also in a non-competitive condition. Hence, difficulty is experienced in realizing high-speed data transfer from an MPU to a signal line driver, and a burden imposed on the MPU increases.
In addition, as conventional techniques regarding a signal line driver incorporating a memory, there have been techniques disclosed in Japanese Unexamined Patent Publication Nos. 10-106254 and 10-105120.
For example, Japanese Unexamined Patent Publication No. 10-106254 discloses a signal line driver capable of rewriting display data in a specified display area.
However, this conventional technique requires that an MPU issues a return command or a writing start command whenever a write address goes beyond an address range in a specified display area, thus leading to an increase in processing load imposed on the MPU. Specifically, in a case in which a liquid crystal display panel has a large screen, this problem becomes serious.
Furthermore, Japanese Unexamined Patent Publication No. 10-105120 discloses the conventional technique in which a monitor circuit monitors whether or not data is read from or written in a memory and, if the read/write thereof is not made from/in the memory, a terminal of an input/output circuit is set at a high-impedance condition.
However, this conventional technique, for its own object, uses only one chip select signal to set an input terminal of an input/output circuit to a high-impedance condition, but it does not achieve an object on speed-up of data transfer or reduction of processing load on an MPU.
The present invention has been developed in consideration of the aforesaid technical objects, and it is an object of the invention to provide a drive unit and a liquid crystal device which are capable of responding exactly to a first access request from a microprocessor side and a second access request from a displaying section side, and further of realizing a high-speed operation and a low-power-consumption operation.
For this object, in accordance with this invention, there is provided a drive unit which receives display data from a microprocessor unit to drive a displaying section, characterized by comprising a memory for storing display data to be used for image display in the displaying section, an arbitration circuit for receiving a first access request forming a request for access to the memory according to a command from the microprocessor unit and a second access request forming a request for access to the memory according to a displaying operation in the displaying section to arbitrate in priority between the first and second access requests for starting an access operation to the memory according to the preferential one of the first and second access requests, and a circuit for outputting, to an external terminal, a memory access monitor signal for monitoring an access condition of the memory to which an access operation starts in accordance with the arbitration of the arbitration circuit.
According to this invention, upon receipt of the first and second access requests, the arbitration circuit arbitrates in the priority between the first and second access requests. When giving the priority to the first access request, the arbitration circuit starts an access operation according to the first access request. On the other hand, when giving the priority to the second access request, it starts an access operation according to the second access request.
In addition, according to this invention, a memory access monitor signal is outputted to an external terminal of the drive unit for monitoring an access condition to the memory. Accordingly, by means of the measurement of a signal level of this memory access monitor signal or variation timing of the signal level, information as to what arbitration is conducted in the arbitration circuit is obtainable through monitoring from the external. In consequence, for example, it is possible to determine a proper generation timing of the first access request.
Still additionally, this invention is characterized in that, when a competition arises between the first and second access requests, the memory access monitor signal becomes active for at least a processing time for a first access operation according to the first access request plus a processing time for a second access operation according to the second access request. In this way, for example, the determination of a proper generation timing of the first access request or the like becomes feasible by merely measuring the length of time for which the memory access monitor signal is active.
Moreover, this invention is characterized in that the memory access monitor signal is a signal to be outputted through the aforesaid external terminal to a wait terminal of the microprocessor unit. This can prolong the time interval between the first access requests only when a competition between the first and second access requests takes place, while it can shorten the time interval therebetween in the normal condition, thus accomplishing a high-speed data transfer.
Still moreover, this invention is characterized by comprising a first control circuit for outputting a signal indicative of the first access request, a second control circuit for outputting a signal representative of the second access request and a third control circuit for outputting a first operation end signal which becomes active at the completion of a first access operation according to the first access request and a second operation end signal which becomes active at the completion of a second access operation according to the second access request, wherein the memory access monitor signal is produced as a logical sum of a signal which becomes active when the first access request signal becomes active while becoming inactive when the first operation end signal becomes active and a signal which becomes active when the second access request signal becomes active while becoming inactive when the second operation end signal becomes active. This allows the memory access monitor signal for monitoring the memory access condition to be developed easily with a small circuit scale by the effective utilization of circuits of the arbitration circuit or the like.
Furthermore, in accordance with this invention, there is provided a drive unit, which receives display data from a microprocessor unit to drive a displaying section, characterized by comprising a memory for storing display data to be used for image display in the displaying section, an arbitration circuit for receiving a first access request forming a request for access to the memory according to a command from the microprocessor unit and a second access request forming a request for access to the memory according to a displaying operation in the displaying section to arbitrate in priority between the first and second access requests for starting an access operation to the memory according to the preferential one of the first and second access requests, a memory control circuit for conducting a precharge operation for the memory before the start of the access operation to the memory, and decision means for making a decision as to whether or not the memory precharge operation reaches completion, wherein the arbitration circuit starts the memory access operation according to one of the first and second access requests on condition that a decision is made to the completion of the memory precharge operation.
According to this invention, the start of the memory access operation takes place provided that the decision shows the completion of the memory precharge operation. Accordingly, the memory access operation can be started at the most suitable timing, thus exhibiting the maximum of ability of the transistors in the drive unit to the utmost. In consequence, the speed-up of the memory access operation becomes achievable.
Still furthermore, this invention is characterized in that the memory control circuit makes a precharge monitor signal active when a decision is made that the memory precharge operation reaches completion, while the arbitration circuit starts the memory access operation according to the first and second access requests on condition that the precharge monitor signal becomes active. The use of this precharge monitor signal permits the effective utilization of circuits included in the arbitration circuit and the control of the memory access operation or the precharge operation.
In addition, this invention is characterized in that the foregoing decision means includes a dummy memory for making a decision as to whether or not the memory precharge operation reaches completion, and the precharge signal is produced by a logical sum of signals of first and second bit lines in the dummy memory. In this way, the precharge monitor signal can be produced with a small circuit scale.
Moreover, in accordance with this invention, there is provided a drive unit, which receives display data from a microprocessor unit to drive a displaying section. characterized by comprising a memory for storing display data to be used for image display in the displaying section, and an address control circuit for, when the microprocessor unit sets a first start address and a first end address related to a first address, forming one address of a column address and a row address of the memory, for access to a specified display area of the memory and starts an access operation to the memory, automatically varying the first address to return the first address to the first start address on condition that the first address goes beyond the first end address and further varying a second address forming the other address of the column address and the row address.
According to this invention, the microprocessor unit first sets the first start address (a column start address or a row start address) of the first address (the column address or the row address) and the first end address (a column end address or a row end address) and then starts the access operation (a write operation or a read operation) to the memory. Accordingly, the first address varies (increments or decrements) automatically, and when the first address goes beyond the first end address, the first address returns to the first start address, while the second address (the row address or the column address) varies, for example, increment takes place by 1. In this way, the speed-up of writing of the display data in the specified display area or the reading of the display data from the specified display area becomes feasible without considerably increasing the processing load on the microprocessor unit.
In addition, this invention is characterized by including first to Nth drive units, with, when an access operation to a memory of an Mth drive takes place, an operating section of each of the other drive units for use on an access operation to its own memory being made inoperative. This can prevent the useless power consumption in the drives other than the Mth drive, thus realizing a low-power-consumption operation.
Still additionally, this invention is characterized in that the first to Nth drive units include first to Nth column address converting circuits, respectively, and further include first to Nth column address control circuits, respectively, with each of the first to Nth column address convening circuits converting a column address set by the microprocessor unit into a relative address to output the converted relative address to the succeeding column address control circuit and further outputting a control signal for validating or invalidating an output of a column address decoder the column address control circuit includes. This enables a reduction of the circuit scale of the column address decoder, which results in a reduction of the circuit scale of the entire drive unit. Additionally, the invalidation of the output of the column address decoder using this control signal prevents the useless power consumption.
Moreover, in accordance with this invention, there is provided a drive unit which receives display data from a microprocessor unit to drive a displaying section, characterized by comprising a memory for storing the display data from the microprocessor unit and an arbitration circuit for receiving a first access request forming a request for access to the memory according to a command from the microprocessor unit and a second access request forming a request for access to the memory according to a displaying operation in the displaying section to arbitrate in priority between the first and second access requests for starting an access operation to the memory according to one of the first and second access requests, wherein, when a competition occurs between the first and second access requests, the arbitration circuit makes an arbitration to always give, priority to the first access request.
According to this invention, when a competition occurs between the first and second access requests, priority is always given to the first access request on the microprocessor unit side. Accordingly, this does not require complicated processing in which the priority to be given to one of the first and second access requests is determined on the basis of the difference in time between these access requests. In consequence, the simplification of the circuit arrangement of an arbitration circuit is feasible and the arbitration circuit in which less malfunction occurs is realizable.
In addition, this invention is characterized in that, when receiving the first access request after the reception of the second access request but before the completion of a second access operation according to the second access request, the arbitration circuit ceases the second access operation while starting a first access operation according to the first access request, and further resumes the second access operation after the completion of the first access operation. In this way, the second access operation according to the second access request is resumable after the first access operation is conducted on the basis of the priority given to the first access request. This enables appropriate time-division access to the memory.
Still additionally, this invention is characterized in that the arbitration circuit includes a holding circuit for holding reservation information about the resumption of the second access operation when receiving the first access request after the reception of the second access request but before the completion of the second access operation according to the second access request, and the arbitration circuit resumes the second access operation on the basis of the reservation information, the holding circuit retains, after the completion of the first access operation. Thus, the installation of the holding circuit for holding the reservation information enables proper resumption of the second access operation after the completion of the first access operation.
Furthermore, a liquid crystal device according to this invention is characterized by comprising any one of the above-described drive units and a liquid crystal display panel driven by that drive unit. The use of the drive unit according to this invention in this way accomplishes scale reduction, power consumption reduction, speed-up of display processing and other advantages of the liquid crystal device, and further allows the liquid crystal device to cope with the screen enlargement of the liquid crystal display panel.